Analysis of TSV-Induced Mechanical Stress and Electrical Noise Coupling in Sub 5-nm Node Nanosheet FETs for Heterogeneous 3D-ICs

Through-silicon via (TSV)-induced mechanical stress and electrical noise coupling effects on sub 5-nm node nanosheet field-effect transistors (NSFETs) were investigated comprehensively compared to fin-shaped FETs (FinFETs) using TCAD for heterogeneous 3D-ICs. TSV-induced channel length directional ( $S_{ZZ}$ ) predominantly causes variations of on-state current $\Delta I_{on}$ ). NSFETs exhibit the greater than FinFETs because electron velocities densities in channels vary with respect same directions but do opposite FinFETs. Nevertheless, is negligible when TSV farther keep-out zone. Meanwhile, signals can be coupled operating devices through substrate induce capacitive back-bias currents $I_{cap}$ , $I_{b-b}$ $\vert I_{cap}\vert /I_{on}$ its wider source/drain (S/D) epitaxies form larger depletion capacitances between drain punch-through stopper (PTS). On other hand, I_{b-b}\vert smaller parasitic bottom transistor alleviates back-bias-induced potential barrier lowering. Furthermore, wide diameter Cu increases only, short rise time both . Unfortunately, conventional cannot satisfy criterion analog applications I_{cap}$ $I_{b-b}\vert /I_{on} %); therefore, a new strategy inserting oxide (BOX) beneath S/D undoped PTS suggested. The decreases by PTS, not due remnant capacitance fin PTS. remarkably completely blocked path, still have path under fin. Therefore, BOX are most suitable 3D-IC, especially applications.